This invention relates to an improvement in a dynamic memory device to reduce its set up time, and to reduce the access time or cycle time of the system employing the memory device.
Among various memory devices used for various kinds of computers or data processing devices, dynamic memory devices especially semiconductor dynamic memory devices are most widely used because of their low cost and stable operation. In order to improve the operation speed of the computers or data processing systems, it is necessary to reduce the access time of the memory device.
A dynamic memory cell must be refreshed periodically to retain its data. Initially, refreshing was done by selecting word lines with an external circuit like the manner of reading data in the memory device. But such an external refreshing method is not easy especially for a large scale memory device, so recently the refreshing has been changed to an internal refreshing method which refreshes the memory cells corresponding to the address generated by an internal address counter.
In such a case, the memory device has to recognize or distinguish a state indicating whether it is required to refresh the stored data or it is required to access the data stored in its memory cells. Such recognition is usually done by discriminating the falling edge of a column address strobe bar signal (CAS bar signal, denoted by CAS) and a row address strobe bar signal (RAS bar signal, denoted by RAS). In particular, if the falling edge of the CAS signal is detected before that of the RAS signal, then the memory device recognizes that refreshing should be done, but if the falling edge of the CAS signal is detected after the falling edge of the RAS signal, the memory device recognizes that it should access the stored data.
Normally, a dynamic memory device is sending or receiving data between its memory cells and external circuits. Thus, reading or writing in the memory is its normal operation. Such operation (usually called as access operation) is controlled by CAS and RAS signals. But during such operation, it also refreshes the data stored in it. The switching of operations is done by advancing or delaying the falling edge of the CAS or RAS signals. These control signals are supplied to the memory device from external circuits. Since the memory devices are fabricated as an IC (integrated circuit) and packed in a single package, these signals are supplied to respective contact pins of the IC.
The refreshing and access operations of a prior art memory device and its problem will be described briefly referring to FIGS. 1 and 2. FIG. 1 is a block diagram to explain the refresh or access operation of a dynamic memory device. In the figure, a detector 1 detects the falling edges of CAS and RAS signals, and discriminates which falling edge of these signals have been detected earlier. The detector 1 sends a refresh signal to a switching circuit 2 when it detects the falling edge of the CAS before that of RAS signal. Therefore, it is called as a CAS before RAS detector.
The switching circuit 2 is supplied an external address 5 and a refresh address 6 which is generated by a refresh address counter 4. The external address 5 is an address of the memory cell in which new data should be read out or rewritten. The external address 5 is supplied through a contact pin of the memory IC. Normally, the switching circuit 2 is switched to the external address signal supplied from an external circuit and sends the signal to an address buffer 3. But when the switching circuit 2 receives the refresh signal, it switches to the refresh address counter 4 to send a refresh address 6 to the address buffer 3.
The address buffer 3 latches the address signals sent from the switching circuit 2, and sends them successively to a word decoder 7. The word decoder selects word lines corresponding to the address signal, and accesses the data in the corresponding memory cells in a memory cell array 8. Since the processes such as decoding and storing the data and reading out the data are conventional and they are not explicitly relevant to the present invention, further description of these processes is omitted.
In a normal access operation, the CAS signal is controlled to become low level after the RAS signal becomes low level L. Therefore, normally the external address is received so that data is stored in or read out from the memory cells, but when the falling edge of the CAS is shifted to go down before RAS, the refresh signal is sent from the detector 1, and the switching circuit 2 sends a refresh address to the address buffer 3, so the stored data is refreshed.
FIG. 2 is a time chart illustrating the operation timing of various points in the circuit of FIG. 1. In the figure, lines above a dashed line show a time relation for normal operation, namely the external address is received, and the lines below the dashed line show a time relation for the refresh operation.
In normal access operation, the CAS signal is at H level, so the detector 1 does not send the refresh signal, and the switching circuit 2 is switched to an external address. When the RAS signal becomes L, it is detected by the address buffer 3, and the address buffer 3 becomes enabled. Then, the external address is latched into the buffer address 3, and is successively sent to a word decoder 7, as address signal A and A. Thus, the data is accessed in the memory array 8. This means the stored data has been accessed.
When it is time for refreshing, as shown by the lines below a dashed line in FIG. 2, timing of the CAS signal is shifted to become L level before the RAS signal is pulled down to L level. Such shifting is done by a shift of a clock pulse or using a delay circuit. This is detected by the detector 1 (which is a CAS before RAS detector), and it sends a refresh signal to the switching circuit. The switching circuit 2 switches the flow of data from external to internal, that is from the external address to a refresh address. Then the RAS signal is pulled down, and the address buffer 3 becomes enabled, so the refresh address is sent to the word decoder and the stored data is refreshed.
As has been described above and as can be seen in FIG. 2, in order to start up the refreshing process in the prior art circuit, it is necessary to pull down the CAS signal, before the RAS signal becomes L. The time between the falling edge of the CAS signal and that of the RAS signal is called a set up time. The set up time should be as short as possible in order to make the access time of the memory system short. Most of the set up time is consumed in detecting the CAS before RAS, sending a refresh signal, receiving the refresh signal and switching the switching circuit. All these processes occur in sequence, so it is impossible to reduce the set up time to less than approximately 20-30 n.sec. using the present-state-of-the-art technology.
Moreover, in usual semiconductor dynamic memory devices, the normal operation of receiving the external data begins with the detection of the falling edge of the RAS signal. So, most of the memory systems using memory devices are designed to begin their operation using the falling edge of the RAS signal as their starting signals. Therefore, a rather complicated process is necessary in order to make the CAS signal become L level before the RAS signal becomes L level, without disturbing the operation of the circuits.
On the other hand, total access time of a usual memory device is approximately 100 n.sec. So, the set up time of 20-30 n.sec. occupies a major portion of the total access time of the memory system. Therefore, the problem of how to reduce the set up time is important in order to reduce the access time of a memory system.